1. Technical Field
The present invention relates generally to bus use or JTAG (Joint Test Action Group) bus use, and particularly to identifying the location of faults on a bus.
2. Description of Related Art
Boundary-scan testing was developed in the mid 1980's to solve physical access problems on printed circuit boards and integrated circuits. Boundary scan, implemented as the JTAG (Joint Test Action Group) interface, embeds test circuitry at the chip level to form a test protocol.
A JTAG bus is a serial bus with four signals: Test Clock (TCK), Test Mode Select (TMS), Test Data Input (TDI), and Test Data Output (TDO). The bus is used for many purposes, including as a test bus for the ‘Boundary-Scan’ of ICs (integrated circuits), as in Design-For-Testability (DFT). To use JTAG, during the design, JTAG compatible devices must be selected. ICs supporting JTAG will have the four additional pins listed above. Devices reside on the bus in a daisy chain, with TDO of one device feeding TDI of the next device.
FIG. 1 shows a block diagram of a typical system with devices (e.g., integrated circuits or chips) that include JTAG compatible devices 104-112 on JTAG bus 114. Microcontroller 102 controls the circuitry for the JTAG bus 114, and can be implemented on board one or more of devices 104-112. Commands are sent to devices 104-112 through the system 100 by shifting bits through the system on the JTAG bus 114 until the proper command is positioned at the target device (e.g., 112). The controller 102 then causes the devices to latch the data that is positioned before them, using the current bit pattern as a command. In this way, devices on the JTAG bus are issued commands without addressing them.
Some conditions that arise create problems on the single chain that are difficult to analyze. For example, a device on the bus can malfunction and pull one or more of the clock signals (TCK, TMS, TDI, or TDO) low. The bus conductors itself can also be faulty, such as when one or more of the bus conductors becomes shorted to a low impedance source such as ground, or when a break occurs in the bus conductors between chips. It would be advantageous to improve current systems for identifying and isolating faults in such cases in an efficient manner.